The present invention relates generally to computer counters, and specifically relates to automatic generation of at-speed binary counters.
A binary counter provides a count signal indicating the number of clock signals received from a CPU clock in a computer. Binary counters have many applications, such as in digital communication systems where a count of the number of clock signals received is used for various purposes by the system. A binary counter typically includes N serially connected stages, each providing an output indicating its state has been changed. The clock signals may be provided synchronously to all stages simultaneously so that the counter output is always correct, or asynchronously to the first stage so that the signal cascades through the stages and the counter output is only correct when the signal has cascaded to the last stage. Outputs from each stage are provided to a decoder array that provides a count signal.
Conventional binary counters suffer important drawbacks. In a typical binary counter, a counting operation is accomplished in response to a counting clock that sends binary count data to a sampling circuit. The circuit first samples count data from the binary counter when a count value signal is read, which is asynchronous with a counting clock signal, and subsequently produces a binary count value. Even if the signal were received when the binary counter performs a counting operation, the circuit outputs the binary count data sampled at the time of the signal occurrence. Since the value attained through the sampling operation is directly outputted from the conventional asynchronous reading circuit, precision of the data cannot be guaranteed.
Additionally, the speed at which binary counters are designed and manufactured using conventional methods can be undesirably low, which can be a serious drawback in an age where electronic devices can quickly become obsolete. Especially for complex Very Deep Sub-Micron VLSI designs, there is a need to reduce the time-to-market to improve profitability. Design flows and synthesis frameworks have been developed to cope with the increasing complexity of the designs and to reduce the time-to-market of a product. However, there is a limit to the benefits of the design flows and synthesis frameworks and therefore reuse of components has been regarded as a key enabler to take advantage of the high-end manufacturing technologies and system design tools. In applications where the length of the binary counters is large and the timing constraints on the counters are aggressive, (e.g., cycle/event counters in a microprocessor or address counters of memory Built-In Self Test modules), the binary counters have to be custom designed. This is a cumbersome and time-consuming process.
A binary counter for counting cycles of a processor clock is described herein. The binary counter includes a fast counter coupled to the processor clock via at least one first clock input, the fast counter incrementing by one after every cycle of the processor clock up to a maximum count. The binary counter further includes a slow counter coupled to the fast counter and to at least one second clock input, wherein the slow counter increments by one after one cycle of the processor clock after the fast counter reaches the maximum count. The slow counter may increment on a rising edge of the processor clock when the fast counter wraps around from its maximum count.
The fast and slow counters can include various combinational logic elements, such as AND and OR gates, and registers connected to the clock inputs. Each register may accept signals via a multiplexer. The slow and fast counters may also include a default reset input to reset the binary counter, and an update data in input to set the binary counter to a value different from zero.
Also described herein is a method for counting cycles of a processor clock including a multi-stage binary counter architecture where the number of stages is greater than two. The first stage is an at-speed counter that counts up for every processor clock. This stage is referred to as the fast counter. The next stage counters do not have to be at speed since every count of one stage counter corresponds to one full count of all of its previous stage counters. Each of these stages is called a slow counter in this document.
Additionally, a computer-readable medium is described herein that stores a program for automatically generating the design for a binary counter for counting cycles of a processor clock. The program includes a fast counter generator for generating a fast counter coupled to the processor clock via at least one first clock input, the fast counter incrementing by one after every cycle of the processor clock up to a maximum count. The program further includes one or more slow counter generators for generating a slow counter coupled to the fast counter and to at least one second clock input, wherein the slow counter increments by one after one cycle of the processor clock after the previous stage counter reaches the maximum count. The computer-readable medium may further include an input file containing a clock rate indicative of a speed of the processor clock and a counter length indicative of a length of the binary counter.